1. Field of the Invention
This invention relates to a method and apparatus for designing circuits and in particular to a method for designing integrated circuits according to a hierarchical block-based design method.
2. Related Art
As circuit design environments become increasingly competitive there is increasing pressure to bring devices implementing the circuits to market quickly and profitably. Todays sub micron technologies may employ processor cores, general purpose circuit blocks and dedicated functional units designed specifically for the intended applications. Integrated circuit designs frequently also include analog circuit blocks such as analog to digital converters, digital to analog converters and phase locked loops. The resulting circuit may incorporate several million gates and would typically operate at clock speeds above 100 MHz. Unnecessary delays in timing convergence or chip assembly are undesirable and can turn out to be costly. Integrated circuit designers working at sub micron dimensions face challenges in implementing and optimizing working chips of such complexity. Circuit design presents considerable difficulties in managing physical implementation to achieve timing convergence. A conventional design process begins with logic synthesis followed by a physical design phase employing place and route procedures. Problems solved during the place and route procedures often require modifications to be made in a further logic synthesis stage and vice versa. Typically iterations through logic synthesis and physical design stages are required.
The definition of a block varies. However in general a block may be regarded as a circuit element comprising anywhere from an individual cell or several cells upwards to thousands of cells. Block-based design methods have been developed to reduce the number of iterations required between logic synthesis and physical implementation stages of integrated circuit design flow. These design methods might employ automatic software tools to generate candidate floorplans for implementing the integrated circuit. The floorplanning tools are integrated with a range of other software tools for designing detailed circuit implementations within each block. Designers can build a floorplan for the integrated circuit by defining high-level descriptions of the blocks. In practice, this is done either by generating new views of blocks or by re-using proven design blocks from previous designs. Block-based design environments allow integrated circuits to be defined in terms of blocks, sub-block descriptions, or actual layouts with parasitics.
Block-based (or hierarchical) design flows reduce the number of iterations required between logical synthesis and physical implementation stages of chip design. Thus in any given design process, a great deal of the time saved is achieved through the use of these automated software tools for designing and updating floorplans. The advantage is that block-based design flows enable concurrent development of the high level design and the individual blocks which make up that design. A problem with existing block-based design flows is that it is difficult to complete blocks of a chip design and join them together, without knowing the detailed internal physical implementation of each block. One reason for this is that silicon MOS devices can be damaged during their fabrication by what is known as the “antenna effect”. Charge which accumulates on exposed metal surfaces (for example during etching processes) can be discharged through MOS gate material which causes yield loss or failures of the silicon product. Circuit design rules include a set of rules which, if followed, protect the circuit from antenna-related problems. Design flows usually include a verification step which checks that these antenna rules have been complied with.
For MOS process technologies, the antenna effect is caused by charge induced sequentially by and in proportion to the amount of exposed metal track connected to a MOS gate at each photo/etch stage. Modern MOS processes use a number of metal interconnect layers and the amount of exposed metal at each metal etch stage is a useful indication of damage probability. Whenever blocks are joined together in block-based design flows, gates within a block can be damaged by antenna effects of the exposed metal external to the block. The charge accumulates at the metal making the internal connection from the port to the MOS gate. Known design flows cannot prevent antenna failures of this type without knowledge of the detailed characteristics of internal and external metal tracking and the amount of gate material connected within a block. Unfortunately this information is not always available early enough in the design process and the result is an antenna failure during high-level design checks. This requires another iteration of the design process, possibly involving an iteration of the sub-block level design. Antenna fails of this type can lead to a significant delay in chip design processes, and due to the random nature of automated place and route flows these iterations may not be convergent towards a solution.
This invention seeks to provide an improved method and apparatus for circuit design with particular applications in integrated circuit design.